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high performance, low power, rail - to - rail precision instrumentation amplifier data sheet AD8422 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power: 33 0 a maximum quiescent current rail - to - rail output low noise and distortion 8 nv/hz maximum input voltage noise at 1 khz 0.15 v p - p rti noise (g = 100) 0.5 ppm nonlinearity with 2 k? load (g = 1) excellent ac specifications 8 0 db minimum cmrr at 7 khz (g = 1) 2.2 mhz bandwidth (g = 1) high precision dc performance ( AD8422 brz) 150 db minimum cmrr (g = 1 000 ) 0.04% maximum gain error (g = 1000) 0. 3 v/ c maximum input offset d rift 0.5 na maximum input bias current wide supply range 3.6 v to 36 v single supply 1.8 v to 18 v dual supply input overvoltage p rotection: 40 v from opposite supply gain range: 1 to 1000 applications medical instrumentation industrial process controls s train ga ges transducer interfaces precision data acquisition systems channel - isolated systems portable instrumentation connection diagram top view (not to scale) 11197-001 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8422 figure 1. 8- lead msop (rm) , 8- lead soic (r) ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 10 100 1k 5k amplitude (dbc) frequency (hz) r l = 2 k? v out = 10 v g = 1000 g = 100 g = 10 g = 1 11197-102 figure 2. total harmonic distortion vs. frequency general description the AD8422 is a high precision, low power , low noise, rail - to - rail instrumentation amplifier that delivers the best performance per unit micro ampere in the industry . the AD8422 processes signals with ultralow distortion performance that is load independent over its full output range. the AD8422 is the third generation development of the industry - standard ad620 . the AD8422 employs new process technologies and design techniques to achieve higher dynamic range and lower errors than its predecessors, while consuming less than one - third of the power. the AD8422 uses the high performance pinout introduced by the ad8221 . ve r y low bias current makes the AD8422 error - free with high source impedance , allowing multiple sensors to be multiplexed to the inp uts . l ow voltage noise and low current noise make the AD8422 an ideal choice for measuring a wheatstone bridge. the wide input range and rail - to - rail output of the AD8422 bring all of the benefits of a high performance in - amp to single - supply applications. whether using high or low supply voltages, the power savings make the AD8422 an excellent choice for high channel count or power sensitive applications on a very tight error budget. the AD8422 uses robust input protection that ensure s reliability without sacrificing n oise p erformance . t he AD8422 has high esd immunity , and the in puts are protected from continuous voltages up to 40 v from the opposite supply rail. a single res istor sets the gain from 1 to 1 000. the ref erence pin can be used to apply a precise offset to the output voltage. the AD8422 is specified from ?40c to +85c and has typical performance curves to 125c. it is available in 8 - lead msop and 8- lead soic packages.
AD8422 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? connection diagram ....................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? soic package ................................................................................ 3 ? msop package .............................................................................. 5 ? absolute maximum ratings ............................................................ 8 ? thermal resistance ...................................................................... 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 19 ? architecture ................................................................................ 19 ? gain selection ............................................................................. 19 ? reference terminal .................................................................... 20 ? input voltage range ................................................................... 20 ? layout .......................................................................................... 20 ? input bias current return path ............................................... 21 ? input voltages beyond the supply rails .................................. 21 ? radio frequency interference (rfi) ........................................ 22 ? applications information .............................................................. 23 ? precision bridge conditioning ................................................. 23 ? process control analog input .................................................. 23 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history 5/13revision 0: initial version
data sheet AD8422 rev. 0 | page 3 of 24 specifications soic package v s = 15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k ?, unless otherwise noted. table 1 . test conditions/ comments AD8422 arz AD8422 brz parameter min typ max min typ max unit common - mode rejection ratio cmrr dc to 60 hz with 1 k? source imbalance v cm = ?10 v to +10 v g = 1 86 94 db g = 10 106 114 db g = 100 126 134 db g = 1000 14 6 15 0 db over temperature, g=1 t = ?40c to +85c 83 89 db cmrr at 7 khz v cm = ?10 v to +10 v g = 1 80 80 db g = 10 90 95 db g = 100 100 10 0 db g = 1000 100 10 0 db noise 1 voltage noise, 1 khz input voltage noise, e ni v in+ , v in? , v ref = 0 v 8 8 nv/ hz output voltage noise, e no 80 80 nv/ hz peak to peak, rti f = 0.1 hz to 10 hz g = 1 2 2 v p - p g = 10 0.5 0.5 v p -p g = 100 to 1000 0.1 5 0.1 5 v p -p current noise f = 1 khz 90 90 110 fa/ hz f = 0.1 hz to 10 hz 8 8 pa p -p voltage offset 2 input offset, v osi v s = 1.8 v to 15 v 60 25 v over temperature t = ?40c to +85c 70 40 v average temperature coefficient 0. 4 0. 3 v/c output offset, v oso v s = 1.8 v to 15 v 300 150 v over temperature t = ?40c to +85c 500 300 v average temperature coefficient 5 2 v/c offset rti vs. supply (psr) v s = 1.8 v to 18 v g = 1 90 110 100 120 db g = 10 110 13 0 1 20 1 4 0 db g = 100 124 15 0 1 40 160 db g = 1000 130 15 0 140 16 0 db input current input bias current v s = 1.8 v to 15 v 0.5 1 0.2 0.5 na over temperature t = ? 40c to +85c 2 1 na average temperature coefficient 4 4 pa/c input offset current v s = 1.8 v to 15 v 0.2 0.3 0. 1 0.15 na over temperature t = ? 40c to +85c 0.8 0.3 na average temperature coefficient 1 1 pa/c
AD8422 data sheet rev. 0 | page 4 of 24 test conditions/ comments AD8422 arz AD8422 brz parameter min typ max min typ max unit reference input r in 20 20 k ? i in v in+ , v in ? , v ref = 0 v 35 50 35 50 a voltage range Cv s +v s Cv s +v s v gain to output 1 1 v/v dynamic response small signal ? 3 db bandwidth g = 1 2200 2200 khz g = 10 85 0 85 0 khz g = 100 12 0 12 0 khz g = 1000 1 2 1 2 khz settling time 0.01% 10 v step g = 1 13 13 s g = 10 13 13 s g = 100 12 12 s g = 1000 80 80 s settling time 0.001% 10 v step g = 1 15 15 s g = 10 15 15 s g = 100 15 15 s g = 1000 1 60 1 60 s slew rate g = 1 to 100 0.8 0.8 v/s gain 3 g = 1 + (19.8 k ? /r g ) g ain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.03 0.01 % g = 10 0.2 0.04 % g = 100 0.2 0.04 % g = 1000 0.2 0.04 % gain nonlinearity v out = ? 10 v to +10 v g = 1 r l = 2 k ? 0.5 5 0.5 5 ppm g = 10 2 5 2 5 ppm g = 100 4 10 4 10 ppm g = 1000 10 20 10 20 ppm gain vs. temperature g = 1 5 1 ppm/c g > 1 ?80 C80 ppm/c input input impedance differential 20 0||2 20 0||2 g ? ||p f common mode 20 0||2 20 0||2 g ? ||p f input operating voltage range 4 v s = 1.8 v to 18 v ?v s + 1.2 +v s ? 1.1 Cv s + 1.2 +v s ? 1.1 v over temperature t = ?40c to +85c ?v s + 1.2 +v s ? 1.2 Cv s + 1.2 +v s ? 1.2 v output output swing , r l = 10 k ? v s = 15 v ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v over temperature t = ?40c to +85c ? v s + 0.25 +v s ? 0.25 ? v s + 0.25 +v s ? 0.25 v output swing , r l = 10 k ? v s = 1.8 v ?v s + 0.12 +v s ? 0.12 ?v s + 0.12 +v s ? 0.12 v over temperature t = ?40c to +85c ?v s + 0.1 3 +v s ? 0 .1 3 ?v s + 0.1 3 +v s ? 0.1 3 v output swing, r l = 2 k ? v s = 15 v ?v s + 0.25 +v s ? 0.25 ?v s + 0.25 +v s ? 0.25 v over temperature 5 t = ?40c to +85c ?v s + 0.3 +v s C 1.4 ?v s + 0.3 +v s C 1.4 v output swing, r l = 2 k ? v s = 1.8 v ?v s + 0.15 +v s ? 0.15 ?v s + 0.15 +v s ? 0.15 v over temperature t = ?40c to +85c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v short- circuit current 20 20 ma
data sheet AD8422 rev. 0 | page 5 of 24 test conditions/ comments AD8422 arz AD8422 brz parameter min typ max min typ max unit power supply operating range dual - supply operation 1.8 18 1.8 18 v single - supply operation 3.6 36 3.6 36 v quiescent current 300 330 300 330 a over temperature t = ? 40c to +85c 400 400 a temperature range specified performance C 40 +85 C 40 +85 c operating range 6 C 40 +125 C 40 +125 c 1 total rti noise = e ni 2 + (e no /g ) 2 2 total rti v os = (v osi ) + (v oso /g). 3 gain does not include the effects of the external resistor, r g . 4 one input grounded. g = 1. 5 output current limited at cold temperatures. see figure 35 . 6 see typical performance characteristics for expected operation between 85c and 125c. msop package v s = 15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k ?, unless otherwise noted. table 2 . test conditions/ comments AD8422 armz ad842 2 brmz parameter min typ max min typ max unit common - mode rejection ratio cmrr dc to 60 hz with 1 k? source imbalance v cm = ? 10 v to + 10 v g = 1 86 90 db g = 10 10 6 11 0 db g = 100 126 13 0 db g = 1000 14 6 15 0 db over temperature, g = 1 t = ?40c to +85c 83 86 cmrr at 7 khz v cm = ?10 v to +10 v g = 1 80 80 db g = 10 90 95 db g = 100 100 10 0 db g = 1000 100 10 0 db noise 1 voltage noise, 1 khz input voltage no ise, e ni v in+ , v in? , v ref = 0 v 8 8 nv/ hz output voltage noise, e no 80 80 nv/ hz peak to peak, rti f = 0.1 hz to 10 hz g = 1 2 2 v p -p g = 10 0.5 0.5 v p -p g = 100 to 1000 0.15 0.15 v p -p current noise f = 1 khz 90 90 110 fa/ hz f = 0.1 hz to 10 hz 8 8 pa p -p voltage offset 2 input offset, v osi v s = 1.8 v to 15 v 70 50 v over temperature t = ?40c to +85c 110 75 v average temperature coefficient 0.6 0.4 v/c output offset, v oso v s = 1.8 v to 15 v 300 150 v over temperature t = ?40c to +85c 500 300 v average temperature coefficient 5 2 v/c
AD8422 data sheet rev. 0 | page 6 of 24 test conditions/ comments AD8422 armz ad842 2 brmz parameter min typ max min typ max unit offset rti vs. supply (psr) v s = 1.8 v to 18 v g = 1 90 110 100 120 db g = 10 110 130 120 140 db g = 100 124 150 140 160 db g = 1000 130 150 140 160 db input current input bias current v s = 1.8 v to 15 v 0.5 1 0.2 0.5 na over temperature t = ? 40c to +85c 2 1 na average temperature coefficient 4 4 pa/c input offset curr ent v s = 1.8 v to 15 v 0.2 0.3 0.1 0.15 na over temperature t = ? 40c to +85c 0.8 0.3 na average temperature coefficient 1 1 pa/c reference input r in 20 20 k ? i in v in+ , v in ? , v ref = 0 v 35 50 35 50 a voltage range ?v s +v s ?v s +v s v gain to output 1 1 v/v dynamic response small signal ? 3 db bandwidth g = 1 2200 2200 khz g = 10 850 850 khz g = 100 120 120 khz g = 1000 12 12 khz settling time 0.01% 10 v step g = 1 13 13 s g = 10 13 13 s g = 100 12 12 s g = 1000 80 80 s settling time 0.001% 10 v step g = 1 15 15 s g = 10 15 15 s g = 100 15 15 s g = 1000 160 160 s slew rate g = 1 to 100 0.8 0.8 v/ s gain 3 g = 1 + (19.8 k ? /r g ) gain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.03 0.01 % g = 10 0.2 0.04 % g = 100 0.2 0.04 % g = 1000 0.2 0.04 % gain nonlinearity v out = ? 10 v to +10 v g = 1 r l = 2 k ? 0.5 5 0.5 5 p pm g = 10 2 5 2 5 ppm g = 100 4 10 4 10 ppm g = 1000 10 20 10 20 ppm gain vs. temperature g = 1 5 1 ppm/c g > 1 ? 8 0 ? 8 0 ppm/c
data sheet AD8422 rev. 0 | page 7 of 24 test conditions/ comments AD8422 armz ad842 2 brmz parameter min typ max min typ max unit input input impedance differential 20 0||2 20 0||2 g ? ||p f common mode 20 0||2 20 0||2 g ? ||p f input operating voltage range 4 v s = 1.8 v to 18 v ?v s + 1.2 +v s ? 1.1 ?v s + 1.2 +v s ? 1.1 v over temperature t = ?40c to +85c ?v s + 1.2 +v s ? 1.2 ?v s + 1.2 +v s ? 1.2 v output output swing, r l = 10 k ? v s = 15 v ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v over temperature t = ?40c to +85c ?v s + 0.25 +v s ? 0.25 ?v s + 0.25 +v s ? 0.25 v output swing, r l = 10 k ? v s = 1.8 v ?v s + 0.12 +v s ? 0.12 ?v s + 0.12 +v s ? 0.12 v over temperature t = ?40c to +85c ?v s + 0.13 +v s ? 0.13 ?v s + 0.13 +v s ? 0.13 v output swing, r l = 2 k ? v s = 15 v ?v s + 0.25 +v s ? 0.25 ?v s + 0.25 +v s ? 0.25 v over temperature 5 t = ?40c to +85c ?v s + 0.3 +v s C 1.4 ?v s + 0.3 +v s C 1.4 v output swing, r l = 2 k ? v s = 1.8 v ?v s + 0.15 +v s ? 0.15 ?v s + 0.15 +v s ? 0.15 v over temperature t = ?40c to +85c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v short- circuit current 20 20 ma power supply operating range dual - supply operation 1.8 18 1.8 18 v si ngle - supply operation 3.6 36 3.6 36 v quiescent current 300 330 300 330 a over temperature t = ?40c to +85c 400 400 a temperature range specified performance C 40 +85 C 40 +85 c operating range 6 C 40 +125 C 40 +125 c 1 total rti noise = e ni 2 + (e no /g ) 2 2 total rti v os = (v osi ) + (v oso /g). 3 gain does not include the effects of the external resistor, r g . 4 one input grounded. g = 1. 5 output current limited at cold temperatures. see figure 35 . 6 see typical performance characteristics for expected operation between 85c and 125c.
AD8422 data sheet rev. 0 | page 8 of 24 abso lute maximum ratings table 3. parameter rating supply voltage 1.8 v to 18 v output short - circuit current duration indefinite maximum voltage at ?in or +in 1 ?v s + 40 v minimum voltage at ?in or +in +v s ? 40 v maximum voltage at ref v s 0.3 v storage temperature range ?65c to +150c operating temperature range ?40c to +125c maximum junction temperature 150c esd human body model 3 kv charge device model 1.25 kv machine model 100 v 1 for voltages beyond these limits, use input protection resistors. see the theory of operation section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; funct ional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. therma l resistance ja is specified for a device in free air using a 4 - layer jedec printed circuit board (pcb). table 4 . package ja unit 8- lead soic 1 00 c/w 8 - lead msop 162 c/w esd caution
data sheet AD8422 rev. 0 | page 9 of 24 pin configuration and function d escriptions top view (not to scale) 11197-002 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8422 figure 3 . pin configuration table 5 . pin function descriptions pin o. neonic description 1 ?in negative input terminal. 2, 3 r g gain setting terminals. place resistor across the r g pins to set the gain. g = 1 + (19.8 k?/r g ). 4 +in positive input terminal. 5 ?v s negative power supply terminal. 6 ref reference voltage terminal. drive this terminal with a low impedance voltage source to level shift the output. 7 v out output terminal. 8 +v s positive power supply terminal.
AD8422 data sheet rev. 0 | page 10 of 24 typical performance characteristics t = 25c, v s = 15, v ref = 0 v , r l = 10 k?, unless otherwise noted. ?90 ?60 ?30 0 30 60 90 0 50 100 150 200 250 300 350 400 input offset vo lt age (v) hits 11197-003 figure 4 . typical distribution of input offset voltage ?900 ?600 ?300 0 300 600 900 0 200 400 600 800 positive input bias current (pa) hits 11197-004 figure 5 . typical distribution of input bias current ?9 ?6 ?3 0 3 6 9 0 100 200 300 400 500 psrr g = 1 (v/v) hits 11197-005 figure 6 . typical distribution of psrr (g = 1) ?300 ?200 ?100 0 100 200 300 0 50 100 150 200 250 300 350 400 output offset vo lt age (v) hits 11197-006 figure 7 . typical distribution of output offset voltage ?300 ?200 ?100 0 100 200 300 0 100 200 300 400 input offset current (pa) hits 11197-007 figure 8. t ypical distribution of input offset current ?40 ?20 0 20 40 0 100 200 300 400 500 cmrr g = 1 (v/v) hits 11197-008 figure 9 . typical distribution of cmrr (g = 1)
data sheet AD8422 rev. 0 | page 11 of 24 ?20 ?15 ?10 ?5 0 5 10 15 20 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode vo lt age (v) output vo lt age (v) g = 1 11197-009 v s = 15 v v s = 1 2v v s = 5v figure 10 . input common - mode voltage vs. output voltage (g = 1), v s = 15 v, v s = 12 v, v s = 5 v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?0.5 0 0.5 1 .0 1.5 2 .0 2.5 3 .0 3.5 4 .0 4.5 5 .0 5.5 input common-mode vo lt age (v) output vo lt age (v) v ref = 0v v ref = 2.5v g = 1 11197-010 fi gure 11 . input common - mode voltage vs. output voltage (g = 1), single - supply , v s = 5 v 0 0.5 1.0 1.5 2.0 2.5 3.0 ?0.5 0 0.5 1 .0 1.5 2 .0 2.5 3 .0 3.5 4 .0 input common-mode vo lt age (v) output vo lt age (v) v ref = 0v v ref = 1.8v g = 1 11197-011 figure 12 . input common - mode voltage vs. output voltage (g = 1), single - supply , v s = 3.6 v ?20 ?15 ?10 ?5 0 5 10 15 20 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode vo lt age (v) output vo lt age (v) 11197-012 v s = 15 v v s = 1 2v v s = 5v g = 100 figure 13 . input common - mode voltage vs. output voltage (g = 100), v s = 15 v, v s = 12 v, v s = 5 v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?0.5 0 0.5 1 .0 1.5 2 .0 2.5 3 .0 3.5 4 .0 4.5 5 .0 5.5 input common-mode vo lt age (v) output vo lt age (v) v ref = 2.5v g = 100 11197-013 v ref = 0v figure 14 . input common - mode voltage vs. output voltage (g = 100), single - supply , v s = 5 v 0 0.5 1.0 1.5 2.0 2.5 3.0 ?0.5 0 0.5 1 .0 1.5 2 .0 2.5 3 .0 3.5 4 .0 input common-mode vo lt age (v) output vo lt age (v) 11197-014 g = 100 v ref = 1.8v v ref = 0v figure 15 . input common - mode voltage vs. output voltage (g = 100), single - supply , v s = 3.6 v
AD8422 data sheet rev. 0 | page 12 of 24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 input current (ma) output vo lt age (v) input vo lt age (v) v s = 5v g = 1 v ref = 2.5v v in? = 2.5v v o ut i in 11197-015 figure 16 . input overvoltage performance; g = 1, v s = 5 v ?20 20 ?15 ?10 ?5 0 5 10 15 ?20 20 ?15 ?10 ?5 0 5 10 15 ?20?25 ?15 ?10 ?5 0 5 10 15 20 25 input current (ma) output vo lt age (v) input vo lt age (v) v s = 1 5v g = 1 v ref = 0v v in? = 0v v o ut i in 11197-016 figure 17 . input overvoltage performance; g = 1 , v s = 15 v ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 input current (ma) output vo lt age (v) input vo lt age (v) v s = 5v g = 100 v ref = 2.5v v in? = 2.5v v o ut i in 11197-017 figure 18 . input overvoltage performance; g = 100, v s = 5 v ?20 20 ?15 ?10 ?5 0 5 10 15 ?20 20 ?15 ?10 ?5 0 5 10 15 ?20?25 ?15 ?10 ?5 0 5 10 15 20 25 input current (ma) output vo lt age (v) input vo lt age (v) v s = 1 5v g = 100 v ref = 0v v in? = 0v v o ut i in 11197-018 figure 19 . input overvoltage performance; g = 100, v s = 15 v ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 ?15 ?10 ?5 0 5 10 15 input bias current (na) common-mode vo lt age (v) 11197-019 v s = 15 v figure 20 . input bias current v s. common - mode voltage, v s = 15 v ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 input bias current (na) common-mode vo lt age (v) 11197-020 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v s = 5v figure 21 . input bias current vs. common - mode voltage , v s = 5 v
data sheet AD8422 rev. 0 | page 13 of 24 0 20 40 60 80 100 120 140 160 180 0.1 1 10 100 1k 10k 100k positive psrr (db) frequenc y (hz) gain = 1 gain = 10 gain = 10 0 gain = 100 0 11197-021 figure 22 . positive psrr vs. frequency 0 20 40 60 80 100 120 140 160 180 0.1 1 10 100 1k 10k 100k neg a tive psrr (db) frequenc y (hz) gain = 1 gain = 10 gain = 10 0 gain = 100 0 11197-022 figure 23 . negative psrr vs. frequency ?20 ?10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) gain = 1 gain = 10 gain = 10 0 gain = 100 0 11197-023 figure 24 . gain vs. frequency 40 60 80 100 120 140 160 180 cmrr (db) frequenc y (hz) gain = 1 gain = 10 gain = 10 0 gain = 100 0 11197-024 0.1 1 10 100 1k 10k 100k figure 25 . cmrr vs. frequency 40 60 80 100 120 140 160 180 cmrr (db) frequenc y (hz) gain = 1 gain = 10 gain = 10 0 gain = 100 0 11197-025 0.1 1 10 100 1k 10k 100k figure 26 . cmrr vs. frequency, 1 k source imbalance ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 60 70 80 90 100 change in input offset vo lt age (v) time (s) 11197-026 figure 27 . change in input offset voltage (v osi ) vs. warm - up time
AD8422 data sheet rev. 0 | page 14 of 24 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 1 10 125 input offset current (na) input bias current (na) tempera ture (c) v s = 15 v normalized a t 25c 11197-027 figure 28 . input bias current and input offset current vs. temperature ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 gain error (v/v) tempera ture (c) represe ntative sam ples norma li zed at 2 5c 11197-028 figure 29 . gain vs. temperature (g = 1) ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 cmrr (v/v) tempera ture (c) 11197-029 repre senta tive sa mple norm ali zed at 2 5c figure 30 . cmrr vs. temperature (g = 1), normalized at 25c 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 supply current (ma) tempera ture (c) 11197-030 figure 31 . supply current vs. temperature (g = 1) ?30 ?20 ?10 0 10 20 30 40 50 60 70 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 shor t -circuit current (ma) tempera ture (c) i short + i shor t ? 11197-031 figure 32 . short - circuit current vs. temperature (g = 1) 0 2 4 6 8 10 12 14 16 18 input voltage (v) referred to supply voltages supply vo lt age (v s ) +v s ?0.5 ?1.0 ?1.5 ?v s +0.5 +1.0 +1.5 ?40 c +25 c +85 c +105 c +125 c 11197-034 figure 33 . input voltage limit vs. supply voltage
data sheet AD8422 rev. 0 | page 15 of 24 0 2 4 6 8 10 12 14 16 18 output vo lt age swing (v) referred t o supp ly vo lt ages supply vo lt age (v s ) +1 25c +8 5c +2 5c ?40 c +v s ?0.1 ?0.2 ?0.3 ?v s +0.1 +0.2 +0.3 11197-035 figure 34 . output voltage swing vs. supply voltage, r l = 10 k 0 2 4 6 8 10 12 14 16 18 output vo lt age swing (v) referred t o supp ly vo lt ages supply vo lt age (v s ) +v s ?0.2 ?0.4 ?0.8 ?0.6 ?v s +0.4 +0.2 +0.6 +0.8 11197-036 +1 25c +8 5c +2 5c ?40 c figure 35 . output voltage swing vs. supply voltage, r l = 2 k ?15 ?10 ?5 0 5 10 15 100 1k 10k 100k output vo lt age swing (v) load resis t ance () 11197-037 ?40 c +25 c +85 c +105 c +125 c figure 36 . output voltage swing vs. load resistance output volta ge s wi ng (v) refe rr ed to supply voltages output current (a) ?0.2 +0 .2 ?0.4 +0 .4 ?0. 6 +0 .6 ?0.8 +0 .8 100 1m 10m +v s ?v s ?40 c +2 5 c +85 c +105 c +125 c 11197-038 figure 37 . output voltage swing vs. output current ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 gain nonlinearity (ppm) output voltage (v) r l = 2k? r l = 10k? v s = 15v g = 1 11197-039 figure 38 . gain nonlinearity (g = 1) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 gain nonlinearity (ppm) output voltage (v) r l = 2k? r l = 10k? v s = 15v g = 10 11197-040 figure 39 . gain nonlinearity (g = 10)
AD8422 data sheet rev. 0 | page 16 of 24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm) output voltage (v) r l = 2k? r l = 10k? v s = 15v g = 100 11197-041 figure 40 . gain nonlinearity (g = 1 00 ) ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm) output voltage (v) r l = 2k? r l = 10k? v s = 15v g = 1000 11197-042 figure 41 . gain nonlinearity (g = 1000) 1 10 100 1k 0.1 1 10 100 1k 10k 100k volt age noise rti (nv/hz) frequenc y (hz) g = 1 g = 10 g = 100 0 g = 10 0 11197-043 figure 42 . voltage noise spectral density vs. frequency 11197-044 g = 1000, 100nv/div 1s/div g = 1, 1v/div figure 43 . 0.1 hz to 10 hz rti voltage noise (g = 1, g = 1000) 10 100 1k 10k 1 10 100 1k 10k current noise (fa/hz) frequenc y (hz) 11197-045 figure 44 . current noise spectral density vs. frequency 11197-046 1s/div 5pa/div figure 45 . 0.1 hz to 10 hz current noise
data sheet AD8422 rev. 0 | page 17 of 24 0 5 10 15 20 25 30 100 1k 10k 100k 1m output vo lt age (v p-p) frequenc y (hz) g = 1 v s = +5v v s = 15 v 11197-047 figure 46 . large signal frequency response 11197-048 13 .6 s to 0. 01 % 15 . 2 s to 0. 001 % 0. 002 %/di v 5v /div 1 0s /div figure 47 . large signal pulse response and settling tim e (g = 1), 10 v step, v s = 15 v , r l = 2 k , c l = 100 pf 11197-049 12.8s to 0. 01 % 15 .1s to 0. 001 % 0. 002 %/div 5v /div 1 0s /div figure 48 . large signal pulse response and settling time (g = 10), 10 v step, v s = 15 v , r l = 2 k , c l = 100 pf 11197-050 1 2.0s to 0.01 % 15 . 2 s to 0. 001 % 0. 002 %/div 5v /div 1 0s /div figure 49 . large signal pulse response and settling time (g = 100), 10 v step, v s = 15 v , r l = 2 k , c l = 100 pf 11197-051 80s to 0. 01 % 160 s to 0.001 % 0. 002 %/div 5v /div 1 00s /div figure 50 . large signal pulse response and settling time (g = 1000), 10 v step, v s = 15 v , r l = 2 k , c l = 100 pf 0 5 10 15 20 25 30 2 4 6 8 10 12 14 16 18 20 settling time (s) step size (v) se ttle d to 0. 01 % se ttle d to 0. 001 % r l = 2 k c l = 100p f 11197-052 figure 51 . settling time vs. step size (g = 1)
AD8422 data sheet rev. 0 | page 18 of 24 11197-053 50mv/div 10s/div figure 52 . small signal pulse response (g = 1), r l = 2 k , c l = 100 pf 11197-054 20mv/div 10s/div figure 53 . small signal pulse response (g = 10), r l = 2 k , c l = 100 pf 11197-055 20mv/div 10s/div figure 54 . sm all signal pulse response (g = 100), r l = 2 k , c l = 100 pf 11197-056 20mv/div 100s/div figure 55 . small signal pulse response (g = 1000), r l = 2 k , c l = 100 pf 11197-057 50mv/div 10s/div no lo ad 20 pf 50 pf 100 pf figure 56 . small signal pulse response with various capacitive loads (g = 1), r l = no load
data sheet AD8422 rev. 0 | page 19 of 24 theory of operation a3 a1 a2 q2 q1 c1 c2 +in ?in +v s ?v s 10k? 10k? 10k? +v s ?v s output ref node 1 node 2 i b compensa tion i b compensa tion r g v b i i +v s +v s +v s 10k? r1 9.9k? r2 9.9k? difference amplifier stage esd and overvoltage protection esd and overvoltage protection super node 3 node 4 super ?v s ?v s 11 197-058 figure 57 . simplified schemati c architecture the AD8422 is based on the classic 3 - op - amp instrumentation amplif ier topology. this topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common - mode voltage. figure 57 shows a simplified schematic of the AD8422 . topologically, q1, a1, r1 and q2, a2, r2 can be viewed as precision current feedback amplifiers that maintain a fixed current in the emitters of q1 and q2 . a ny change in the input signal forces the outp ut voltages of a 1 and a2 to change accord - ingly and maintain the q1 and q2 current at the correct value. this causes a precise diode drop from C in and +in to node 3 and node 4 , respectively, so that t he differential signal applied to the inputs is replicat ed across the r g pins. any current through r g must also flow through r1 and r2, creating the gained differential voltage between node 1 and node 2. the amplified differential signal and the common - mode s ignal are applied to a difference amplifier that reje cts the common - mode voltage but preserves the amplified differential voltage. laser - trimmed resistors allow for a highly accurate in - amp with a gain error of less than 0.01% and a cmrr that exceeds 94 db (g = 1). the supply current is precisely trimmed to reduce uncertainties due to part - to - part variations in power dissipation and noise. the high performance pinout and special attention to design and layout allow for high cmrr across a wide frequency and temperature range. using superbeta input transistors and bias current compensation, the AD8422 offers extremely high input impedance and low bias cur rent, as well as very low voltage noise while using only 3 0 0 a supply current . the overvoltage prot ection scheme allow s the input to go 40 v from the opposite rail at all gains without compromising the noise performance. the transfer function of the AD8422 is v out = g ( v in+ ? v in? ) + v ref whe re: g r g k19.8 1 += gain selection placing a resistor across the r g terminals sets the gain of the AD8422 that can be calculated by referring to table 6 or by using the following gain equation: 1 k19.8 ? = g r g the AD8422 defaults to g = 1 when no gain resistor is used. add the tolerance and gain drift of the r g resistor to the specifications of the AD8422 to determine the total gain accuracy of the system. when the gain resistor is not used, gain error and gain drift are minimal. table 6 . gains achieved using 1% resistor s 1% standard table value of r g (?) calculated gain 19.6 k 2.010 4.99 k 4.968 2.21 k 9.959 1.05 k 19.86 402 50.25 200 100 .0 100 199.0 39.2 506.1 20 991.0
AD8422 data sheet rev. 0 | page 20 of 24 r g power dissipation the AD8422 duplicates the differential voltage across its inputs onto the r g resistor. choose an r g resistor size that is sufficient to handle the expected power dissipation at ambient temperature. reference terminal the output voltage of the AD8422 is developed with respect to the potential on the reference terminal. this can be used to apply a precise offset to the output signal. for example, a voltage source can be tied to the ref pin to level shift the output, allowing the AD8422 to drive a unipolar analog-to-digital converter (adc). the ref pin is protected with esd diodes and must not exceed either +v s or ?v s by more than 0.3 v. for best performance, maintain a source impedance to the ref terminal that is below 1 . as shown in figure 57, the reference terminal, ref, is at one end of a 10 k resistor. additional impedance at the ref terminal adds to this 10 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be calculated as 2(10 k + r ref )/(20 k + r ref ) only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct AD8422 op1177 + ? v ref AD8422 ref 11197-059 figure 58. driving the reference pin (ref) input voltage range the 3-op-amp architecture of the AD8422 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. internal nodes between the first and second stages (node 1 and node 2 in figure 57) experience a combination of a gained signal, a common-mode signal, and a diode drop. the voltage supplies can limit the combined signal, even when the individual input and output signals are not limited. figure 10 through figure 15 show this limitation in detail. layout to ensure optimum performance of the AD8422 at the pcb level, take care in the design of the board layout. to aid in this task, the pins of the AD8422 are arranged in a logical manner. top view (not to scale) 11197-060 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8422 figure 59. pinout diagram common-mode rejection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to maintain high cmrr over frequency, closely match the input source imped- ance and capacitance of each path. place additional source resistance in the input path (for example, for input protection) close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins (r g ) can also affect cmrr over frequency. if the board design has a component at the gain setting pins (for example, a switch or jumper), choose a component such that the parasitic capacitance is as small as possible. power supplies and grounding use a stable dc voltage to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. place a 0.1 f capacitor as close as possible to each supply pin. because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. a parasitic inductance in the bypass ground trace works against the low impedance created by the bypass capacitor. as shown in figure 60, a 10 f capacitor can be used farther away from the device. for larger value capacitors, intended to be effective at lower frequencies, the current return path distance is less critical. in most cases, this capacitor can be shared by other local precision integrated circuits. AD8422 + v s +in ?in load r g ref 0.1f 10f 0.1f 10f ?v s v out 11197-061 figure 60. supply decoupling, ref, and output referred to local ground
data sheet AD8422 rev. 0 | page 21 of 24 a ground plane layer is helpful to reduce parasitic inductances. this minimizes voltage drops with changes in current. the area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequencies. large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. because load currents flow from the supplies, connect the load at the same physical location as the bypass capacitor grounds. reference pin the output voltage of the AD8422 is developed with respect to the potential on the reference terminal. ensure that ref is tied to the appropriate local ground. input bias current return path the input bias current of the AD8422 must have a dc return path to ground. when using a floating source without a current return path, such as a thermocouple, create a current return path, as shown in figure 61. thermocouple +v s ref ?v s AD8422 capacitively coupled +v s ref c c ?v s AD8422 transformer +v s ref ?v s AD8422 incorrect capacitively coupled +v s ref c r r c ?v s AD8422 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? AD8422 transformer +v s ref ?v s AD8422 correct 11197-062 figure 61. creating an inpu t bias current return path input voltages beyond the supply rails many instrumentation amplifiers specify excellent cmrr and input impedance, but in a real system, the performance suffers because of the external components required for input protection. the AD8422 has very robust inputs. it typically does not need additional input protection. input voltages can be up to 40 v from the opposite supply rail without damage to the part. for example, with a +5 v positive supply and a 0 v negative supply, the part can safely withstand voltages from ?35 v to +40 v. unlike some other instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. most applications + v s AD8422 ?v s i v in+ + ? v in+ + ? 11197-063 figure 62. input overvoltage protecti on with no external components for input voltages less than 40 v from the opposite rail, no input protection is required. keep the rest of the AD8422 terminals within the supplies. all terminals of the AD8422 are protected against esd. input voltages beyond the maximum ratings for applications where the AD8422 encounters voltages beyond the limits in the absolute maximum ratings section, external protection is required. this external protection depends on the duration of the overvoltage event and the noise performance required. for short-lived events, transient protectors such as metal oxide varistors (movs) may be all that is required. for longer events, use resistors in series with the inputs combined with diodes. to avoid worsening bias current performance, low leakage diodes, such as the bav199 or fjh1100s, are recommended. the diodes prevent the voltage at the input of the amplifier from exceeding the maximum ratings, while the resistors limit the current into the diodes. because most external diodes can easily handle 100 ma or more, resistor values do not have to be large. therefore, the protection resistance has minimal impact on noise performance.
AD8422 data sheet rev. 0 | page 22 of 24 + v s AD8422 ?v s v in+ + ? v in? + ? + v s AD8422 r protect r protect ?v s i v in+ + ? v in? + ? +v s +v s AD8422 r protect r protect ?v s ?v s i v in+ + ? v in? + ? +v s ?v s +v s AD8422 r protect r protect ?v s i v in+ + ? v in? + ? i simple continuous protection transient protection low noise continuous option 2 low noise continuous option 1 11197-064 figure 63. input protection options fo r input voltages beyond absolute maximum ratings at the expense of some noise performance, another solution is to use series resistors. in the overvoltage case, current into the inputs of the AD8422 is internally limited to a safe value for the amplifier. although the AD8422 inputs must still be kept within the absolute maximum ratings, the i r drop across the protection resistor increases the maximum voltage that the system can withstand to the following values: for positive input signals, v max_new = (40 v + negative supply ) + i in r protect for negative input signals, v min_new = ( positive supply C 40 v) ? i out r protect overvoltage performance is shown in figure 16, figure 17, figure 18, and figure 19. with gains greater than 100 and supply voltages less than 2.5 v, overdrive voltages beyond the rails may cause the output to invert as far as the ref pin voltage. radio frequency interference (rfi) rf rectification is often a problem when amplifiers are used in applications that have strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low-pass rc network placed at the input of the instrumentation amplifier, as shown in figure 64. r r AD8422 + v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s r g c d 10nf c c 1nf c c 1nf 2k ? 2k ? 11197-065 figure 64. rfi suppression the filter limits the input signal bandwidth, according to the following relationship: )2(2 1 c d diff ccr uency filterfreq ? ? c cm rc uency filterfreq 2 1 ? where c d 10 c c . c d affects the difference signal, and c c affects the common-mode signal. choose values of r and c c that minimize rfi. a mismatch between r c c at the positive input and r c c at the negative input degrades the cmrr of the AD8422 . by using a value of c d that is one order of magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved. resistors add noise; therefore, the choice of the resistor and capacitor values depends on the desired tradeoff between noise, input impedance at high frequencies, and rf immunity. the resistors used for the rfi filter can be the same as those used for input protection.
data sheet AD8422 rev. 0 | page 23 of 24 applications information precision bridge conditioning with its high cmrr, low drift, and rail-to-rail output, the AD8422 is an excellent choice for conditioning a signal from a wheatstone bridge. with appropriate supply voltages, the gain and reference pin voltage can be adjusted to match the full-scale bridge output to any desired output range, such as 0 v to 5 v. figure 65 shows a circuit to convert a bridge signal into a 4 ma to 20 ma output using the ad8276 low power, precision difference amplifier, and the ada4096-2 low power, rail-to-rail input and output, overvoltage protected op amp. with high precision bridge circuits, care must be taken to compensate offsets and temperature errors. for example, if the voltage at the ref pin is used to compensate for the bridge offset, ensure that the AD8422 is within its operating range for the maximum expected offset. if the zero- adjust potentiometer is excluded, connect the positive op amp input to the center of the 24.9 k, 10.7 k divider, which is at 1.5 v. if lower supply voltages are used for the ad8276 and the ada4096-2 , ensure that the desired output voltage of the ad8276 is within its output range, and v l is within the input and output range of the ada4096-2 . the transistor must have sufficient breakdown voltage and i c . low cost transistors, such as the bc847 or 2n5210, are recommended. process control analog input in process control systems such as programmable logic controllers (plc) and distributed control systems (dcs), analog variables typically occur in just a few standard voltage or current ranges, including 4 ma to 20 ma and 10 v. variables within these input ranges must often be gained or attenuated and level shifted to match a specific adc input range such as 0 v to 5 v. the circuit in figure 66 shows one way this can be done with a single AD8422 . low power, overvoltage protection, and high precision make the AD8422 a good match for process control applications, and high input impedance, low bias current, and low current noise allow significant source resistance with minimum additional errors. +5 v +5v +5v ref ref sense +24v +24v +24v +24v +in 10.7k ? 24.9k ? 124 ? 1 1 optional zero adjust ?in +in ?in v out_fs = 15mv i out = 4ma to 20ma v = 0.5v to 2.5v r l v l r g = 301 ? g = 66.8v/v r g v out AD8422 ada4096-2 ad8276 ada4096-2 11197-066 figure 65. bridge circuit with 4 ma to 20 ma output +15v ?15v 2.5v ref +in 42.2k ? 0v to 10v, 10v termin a l block 0v to 5v, 5v 0v to 1v, 1v 4ma to 20ma, 0ma to 20ma 20ma 34k ? 8.45k ? 1k ? 1k ? 49.9k ? ?in r g AD8422 r g = 13.2k ? g = 2.5v/v v out = 2.5v 2.5v 11197-067 figure 66. process control analog input
AD8422 data sheet rev. 0 | page 24 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 67. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 68. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding AD8422arz ?40c to +85c 8-lead soic_n, standard grade r-8 AD8422arz-r7 ?40c to +85c 8-lead soic_n, standard grade, 7 tape and reel, r-8 AD8422arz-rl ?40c to +85c 8-lead soic_n, st andard grade, 13 tape and reel r-8 AD8422brz ?40c to +85c 8-lead soic_n, high performance grade r-8 AD8422brz-r7 ?40c to +85c 8-lead soic_n, high performance grade, 7 tape and reel r-8 AD8422brz-rl ?40c to +85c 8-lead soic_n, high performance grade, 13 tape and reel r-8 AD8422armz ?40c to +85c 8-lead msop, standard grade rm-8 y4u AD8422armz-r7 ?40c to +85c 8-lead msop, stan dard grade, 7 tape and reel, rm-8 y4u AD8422armz-rl ?40c to +85c 8-lead msop, stan dard grade, 13 tape and reel rm-8 y4u AD8422brmz ?40c to +85c 8-lead msop, high performance grade rm-8 y4v AD8422brmz-r7 ?40c to +85c 8-lead msop, high performance grade, 7 tape and reel rm-8 y4v AD8422brmz-rl ?40c to +85c 8-lead msop, high performance grade, 13 tape and reel rm-8 y4v 1 z = rohs compliant part. ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11197-0-5/13(0)

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